View W83L518D_52735.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Winbond Integrated Media Reader W83L518D Datasheet
W83L518D Data Sheet Revision History
Version on Web 1.0 1st Release
Pages 1 2 3 4 5 6 7 8
Dates 02/Jul.
Version 1.0
Main Contents
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
CONTENT
1 2 GENERAL DESCRIPTION ....................................................................................................... 1 FUNCTIONS ...........................................................................................................................2
2.1 GENERAL................................................................................................................................... 2 2.2 SMART CARD INTERFACE.............................................................................................................. 2 2.3 MEMORY STICK INTERFACE............................................................................................................ 2 2.4 SD MEMORY CARD INTERFACE....................................................................................................... 2 2.5 PACKAGE.................................................................................................................................. 2 3 4 PIN CONFIGURATION FOR W83L518D ...................................................................................3 PIN DESCRIPTION .................................................................................................................4
4.1 BUS INTERFACE...........................................................................................................................4 4.2 SMART CARD INTERFACE PINS ....................................................................................................... 5 4.3 MEMORY STICK INTERFACE/SD MEMORY INTERFACE PINS.................................................................... 6 4.4 GENERAL-PURPOSE I/O PINS .........................................................................................................7 4.5 CRYSTAL AND POWER PINS ..........................................................................................................7 5 6 GENERAL-PURPOSE I/O PORTS (GPIO) .................................................................................8 CONFIGURATION REGISTER ............................................................................................... 10
6.1 PLUG AND PLAY CONFIGURATION................................................................................................. 10 6.2 COMPATIBLE PNP...................................................................................................................... 10 6.2.1 Extended Function Register............................................................................................... 10 6.2.2 Extended Functions Enable Register (EFER) ...................................................................... 11 6.2.3 Extended Function Index Register (EFIR), Extended Function Data Register (EFDR) .............. 11 6.3 CONFIGURATION SEQUENCE......................................................................................................... 11 6.3.1 Software programming example.......................................................................................... 12 6.4 GLOBAL REGISTERS................................................................................................................... 12 6.5 LOGICAL DEVICE 0 (SMART CARD INTERFACE) ................................................................................. 15 6.6 LOGICAL DEVICE 1 (MEMORY STICK INTERFACE)............................................................................... 15 6.7 LOGICAL DEVICE 2 (GPIO) .......................................................................................................... 16 6.8 LOGICAL DEVICE 3 (SD MEMORY INTERFACE) .................................................................................. 18 7 8 9 10 ORDERING INSTRUCTION.................................................................................................... 19 HOW TO READ THE TOP MARKING ..................................................................................... 19 PACKAGE DRAWING AND DIMENSIONS .............................................................................. 20 THE W83L518D SCHEMATIC............................................................................................. 22
W83L518D
1
GENERAL DESCRIPTION
W83L518D is Winbond's innovative solution to a new class of storage devices for IA Noetebook, Desktop PC and PC system-related products. It incorporates a security Application: Smart Card Interface and two most promising compact storage interfaces: Memory Stick interface, and SD Memory Card/Multimedia Card interface in IT era. To cater boundless IT implementation possibilities, W83L518D can be configured to interface with host through LPC bus. Base on the LPC interface, one Smart Card Interface port and two flash memory interfaces - Memory Stick and SD Memory ports are provided. The kind of versatility allows user to design very cost-effective products in a very flexible way. The whole chip of W83L518D operates at voltage level of 3.3 V except Smart Card Interface port's I/O pins that are at 5 V to be compatible with mainstream Smart Card implementations. Advanced power
management feature further optimizes power consumption whether in operation or in power down mode. W83L518D comes as a 48-pin LQFP streamline package. Combining with powerful functions, effective power management, and versatile configurability, this integrated media reader offers a perfect approach for design of storage device of IT products. The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation. Information check: http://www.memorystick.org/ The trademarks and intellectual property rights of Secure Digital belong to SD Group. Information check: http://www.sdcard.org/
The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners
1
Publication Release Date:Jul. 2002 Revision 1.0
W83L518D
2
FUNCTIONS
2.1 General
q LPC bus is compliant with LPC Spec. 1.01 q LPC bus supports LDRQ# (LPC DMA), SERIRQ (serial IRQ) q Programmable configuration settings q 48 MHz crystal inputs q PCICLK of 33 MHz is needed for LPC bus configuration
2.2 Smart Card Interface
q ISO-7816 compliant q PC/SC T=0, T=1 compliant q 16-byte transmitter FIFO and 16-byte receiver FIFO q FIFO threshold interrupt to optimize system performance q Programmable transmission clock frequency q Versatile baud rate configuration q UART-like register file structure q General-purpose C4, C8 channels
2.3 Memory Stick Interface
q Memory Stick Standard Format Specifications ver. 1.3 compliant q Support interrupt polling transmission q Support FIFO threshold interrupt to optimize system performance q Automatic clock halt to prevent underrun/overrun q 16 MHz interface clock
2.4 SD Memory Card Interface
q SD Memory Card Specifications: Part 1 PHYSICAL LAYER SPECIFICATION Version 1.0 Compliant q Support interrupt polling transmission q Support FIFO threshold interrupt to leverage system performance q 24 MHz interface clock
2.5 Package
q 48-pin LQFP
The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners
2
Publication Release Date:Jul. 2002 Revision 1.0
W83L518D
3
PIN CONFIGURATION FOR W83L518D
SDPWR#/GP21
SDLED/GP20 SCC4
MSLED MSPWR# VSS
MSCLK MS1 29 28
SCC8
MS2 27
36
35 34
33
32 31
30
SDCLK /GP22 SD1 /GP23 SD2 /GP24 VDD3V SD3 /GP25 SD4 /GP26 SD5 /GP27 LAD3 LAD2 LAD1 LAD0 SERIRQ
37 38 39 40 41 42 43 44 45 46 47 48 1
26 25 24 23 22 21 20 19 18 17 16 15 14 13
MS3 MS4
W83L518D
MS5 XIN XOUT SCRST# SCIO SCCLK SCPSNT SCPWR# SCLED VDD GP10 GP11
10 GP14
LDRQ# LFRAME#
PME# VSS
GP17
GP16 GP15
PCICLK
RESET#
The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners
3
GP13 GP12
Publication Release Date:Jul. 2002 Revision 1.0
11 12
2 3
4
5 6
7
8 9
W83L518D
4
Note: INt INtp3 INts
PIN DESCRIPTION
- 5V TTL level input pin - 3.3V TTL level input pin - 5V TTL level Schmitt-trigger input pin - 3.3V TTL level Schmitt-trigger input pin - 5V TTL level bi-directional pin with 12 mA drive-sink capability - 5V TTL level bi-directional pin with 24 mA drive-sink capability - 3.3V TTL level bi-directional pin with 16 mA drive-sink capability - 5V output pin with 2 mA drive-sink capability - 5V output pin with 12 mA drive-sink capability - 3.3V output pin with 16 mA drive-sink capability - 3.3V Open-drain output pin with 12 mA sink capability.
INtsp3 I/O12t I/O24t I/O16tp3 O2 O12 O16p3 OD12p3
4.1 Bus Interface
SYMBOL PME# RESET# LFRAME# LDRQ# PCICLK SERIRQ LAD0 LAD1 46 LAD2 45 LAD3 44 I/O16tp3 I/O16tp3 PIN 5 4 3 2 1 48 47 I/O16tp3 I/O OD12p3 INtsp3 INtsp3 O16p3 Intsp3 I/O16tp3 I/O16tp3 FUNCTION Active-low PME event. Active-low system reset signal. Active-low signal indicates start of a new LPC frame or termination of a premature frame. Encoded DMA Request signal. PCI clock input of 33 MHz. Serial IRQ input/output. This signal combining with other LADx signals communicate address, control, and data information over the LPC bus between a host and a peripheral. This signal combining with other LADx signals communicate address, control, and data information over the LPC bus between a host and a peripheral. This signal combining with other LADx signals communicate address, control, and data information over the LPC bus between a host and a peripheral. This signal combining with other LADx signals communicate address, control, and data information over the LPC bus between a host and peripherals.
The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners
4
Publication Release Date:Jul. 2002 Revision 1.0
W83L518D
4.2 Smart Card Interface Pins
SYMBOL SCC4 PIN 34 I/O I/O16tp3 I/O16tp3 FUNCTION Smart Card interface general purpose I/O channel for connector pin C4 on a card. Smart Card interface general purpose I/O channel for connector pin C8 on a card. This pin outputs an oscillating clock signal of various frequencies depending on traffic of primary Smart Card interface. Smart Card interface power control signal. Smart Card interface card present detection Schmitt-trigger input. Smart Card interface clock output. Smart Card interface data I/O channel. Smart Card interface reset output.
SCC8
33
SCLED SCPWR# SCPSNT SCCLK SCIO SCRST#
16 17 18 19 20 21
O24 O24 INts O2 I/O12t O12
The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners
5
Publication Release Date:Jul. 2002 Revision 1.0
W83L518D
4.3 Memory Stick Interface/SD Memory Interface Pins
SYMBOL MSLED MSPWR# MSCLK MS1 MS2 MS3 MS4 MS5 SD5 SD interface pin. SD interface pin. SD interface pin. SD interface pin. SDCLK SDPWR# SDLED CARD_DETECT PIN 32 31 29 28 27 26 25 24 43 42 41 39 38 37 36 35 13 I/O O16p3 O16p3 O16p3 O16p3 I/O16tp3 --INtsp3 --I/O16tp3 I/O16tp3 I/O16tp3 I/O16tp3 I/O16tp3 O16p3 O16p3 O16p3 INt FUNCTION Memory Stick function - This pin outputs an oscillating clock signal of various frequencies depending on traffic of the Memory Stick interface. Memory Stick function - This pin is power control signal for the Memory Stick interface. Memory Stick function - This pin is SCLK for the Memory Stick interface. Memory Stick interface pin. Memory Stick interface pin. Memory Stick interface pin. Memory Stick interface pin. Memory Stick interface pin. SD interface pin. SD interface pin. SD interface pin. SD interface pin. SD interface pin. SD function - This pin is CLK for the SD memory card interface. SD function - This pin is power control signal for the SD memory card interface. SD function - This pin outputs an oscillating clock signal of various frequencies depending on traffic of the SD memory card interface. Function as an alternative card detection input for the SD memory interface.
The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners
6
Publication Release Date:Jul. 2002 Revision 1.0
W83L518D
4.4 General -Purpose I/O Pins
SYMBOL GP17 GP16 GP15 GP14 GP13 GP12 GP11 EX_CD PIN 7 8 9 10 11 12 13 I/O I/O12t I/O12t I/O12t I/O12t I/O12t I/O12t I/O12t FUNCTION General-purpose I/O port 17. General-purpose I/O port 16. General-purpose I/O port 15. General-purpose I/O port 14. General-purpose I/O port 13. General-purpose I/O port 12. General-purpose I/O port 11. External card detedtion pin. The detectable level can be set on bit 2 of CR F0 on Logical device 3. GP10 PHEFRAS 14 I/O12t Int General-purpose I/O port 10. This pin also functions as a power-on setting pin whose value is latched on the rising edge of RESET# (pin 4) to select configuration ports as 2 Eh/2Fh (PHEFRAS = 1) or 4Eh/4Fh (PHEFRAS = 0). It determines the default value of CR26 bit 6 (HEFRAS).
4.5 Crystal and Power Pins
SYMBOL XOUT, XIN PIN 22, 23 FUNCTION Connected to a 48 MHz crystal and function as the working clock for all the media reader interfaces. VDD3V 40 +3.3V power supply for host interface, Memory Stick/SD Memory interfaces, and internal core. VDD VSS 15 6, 30 +5V power supply for Smart Card interface I/O pins. Ground.
The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners
7
Publication Release Date:Jul. 2002 Revision 1.0
W83L518D
5
GENERAL-PURPOSE I/O PORTS (GPIO)
W83L518D supports one group of dedicated general-purpose I/O ports and a multi-functional GPIO group, which share the same pines with the SD interface sockets. There are cases when only one socket is needed in a system and pins for the other unused socket are wasted. To provide the most cost-effective solution, W83L518D could be configured to transform these pins into general-purpose I/O ports. The first group (GP10 ~ 17) is configured through the configuration registers CRF0 ~ CRF2 in logical device 2 and the other group (GP20 ~27) through CRF3 ~ F5. Users can configure each individual port to be an input or output port by programming respective bit in direction register (CRF0/CRF3: 0 = output, 1 = input). Invert port value by setting inversion register (CRF2/CRF5: 0 = non-inverse, 1 = inverse). Port value is read/written through data register (CRF1/CRF4). Table 5.1 and 5.2 illustrate GPIO's assignment. To further facilitate system design, W83L518D allows direct accesses to data register and direction register through I/O ports, whose base address is programmable at CR 60, 61 in logical device 2. Detailed configuration is described in logical device 2 of section 6: CONFIGURATION REGISTER. GP10 (pin 14) also functions as a power-on setting pin whose value is latched on the rising edge of RESET# (pin 4) to select configuation port addresses. Therefore, GP10 is a push-pull I/O port unlike the other GPIO ports, which are open-drained I/Os to support this power-on setting feature. GP11 (pin 13) could function as a card detection input if selected by SDI to support some MMC cards, which don't offer card detection feature through DATA3 pin.
Table 5.1 DIRECTION BIT 0 = OUTPUT 1 = INPUT 0 0 1 1 INVERSION BIT 0 = NON INVERSE 1 = INVERSE 0 1 0 1 I/O OPERATION
Basic non-inverting output Basic inverting output Basic non-inverting input Basic inverting input
The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners
8
Publication Release Date:Jul. 2002 Revision 1.0
W83L518D
Table 5.2 GPIO PORT DATA REGISTER REGISTER BIT ASSIGNMENT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 GP I/O PORT GP10 GP11 GP12 GP13 GP14 GP15 GP16 GP17 GP20 GP21 GP22 GP23 GP24 GP25 GP26 GP27
GP1
GP2
The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners
9
Publication Release Date:Jul. 2002 Revision 1.0
W83L518D
6
CONFIGURATION REGISTER
6.1 Plug and Play Configuration
W83L518D/W83L519D implement compatible PNP protocol to access configuration registers for setting up different types of configurations. There are four Logical Devices (Logical Device 0 to Logical Device 3) in W83L518D/W83L519D which correspond to four major functions: Smart Card Interface (logical device 0), Memory Stick Interface (logical device 1), GPIO (logical device 2) and SD Memory Interface (logical device 3). Each Logical Device has its own configuration registers (CR30 and above). Host can access those registers by writing an appropriate logical device number into logical device select register at CR07 first. 07h logical device select 30h logical device control 3Fh 40h logical device configuration One set per logical device
global registers
FEh
6.2 Compatible PnP
6.2.1 Extended Function Register W83L518D/W83L519D provide two methods to enter Extended Function m ode (compatible PnP) and access configuration registers dependent on value of HEFRAS (bit 6 of CR26. The corresponding poweron setting pin is pin 14) as follows: HEFRAS 0 1 address and value write 83h to I/O address 2Eh twice write 83h to I/O address 4Eh twice
In Compatible PnP, a specific value (83h) must be written twice to the Extended Function Enable Register (EFER at I/O address 2Eh or 4Eh). Secondly, an index value (02h, 07h-FFh) must be written to the Extended Function Index Register (EFIR, I/O address at 2Eh or 4Eh which is the same as EFER) to
The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners
10
Publication Release Date:Jul. 2002 Revision 1.0
W83L518D
identify which configuration register is to be accessed. User can then access the addressed
configuration register through the Extended Function Data Register (EFDR, I/O address at 2Fh or 4Fh). After programming of the configuration register is completed, another specific value (0AAh) should be written to EFER to leave Extended Function mode to prevent inadvertent accesses to those configuration registers. User may write a "1" to bit 5 of CR26 (LOCKREG) to prevent configuration registers from accidental accesses. 6.2.2 Extended Functions Enable Register (EFER) After a power-on reset, W83L518D/W83L519D enters the default operation mode. A specific value must be programmed into the Extended Function Enable Register (EFER) so that configuration registers can be accessed. On a PC/AT system, its I/O address is 2Eh or 4Eh (as described in previous section). 6.2.3 Extended Function Index Register (EFIR), Extended Function Data Register (EFDR) After entering Extended Function mode, Extended Function Index Register (EFIR) must be written with an index value (02h, 07h-FEh) to specify which configuration register is to be accessed through Extended Function Data Register (EFDR). EFIR is a write-only register at I/O address 2Eh or 4Eh (as described in section 9.2.1) on a PC/AT system and EFDR is a read/write register at I/O address 2Fh or 4Fh.
6.3 Configuration Sequence
To program configuration registers, specific configuration sequence must be followed: (1) Write 83h to EFER twice to enter Extended Function mode. (2) Select logical device select register by writing 07h to EFIR. (3) Select logical device by writing a value to EFDR. (4) Select control/configuration register by writing its index to EFIR. (5) Access selected control/configuration register through EFDR. (6) Repeat step 4 ~ 5 as needed. (7) Leave Extended Function mode by writing AAh to EFER. Step 2 and step 3 are not necessary for accessing global register (index 00h to 2Fh).
The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners
11
Publication Release Date:Jul. 2002 Revision 1.0
W83L518D
6.3.1 Software programming example The following example is written in Intel 8086 assembly language. EFER and EFIR are assumed to be at 2Eh, and EFDR is at 2Fh. Use 4Eh/4Fh instead of 2Eh/2Fh if HEFRAS (bit 6 of CR26) is set. ;----------------------------------------------------------------------------------; Enter Extended Function mode, interruptible double-write | ;----------------------------------------------------------------------------------MOV DX, 2Eh MOV AL, 83h OUT DX, AL OUT DX, AL ;----------------------------------------------------------------------------; Configure logical device 1, configuration register CRF0 | ;----------------------------------------------------------------------------MOV DX, 2Eh MOV AL, 07h OUT DX, AL ; point to Logical Device Number Reg. MOV DX, 2Fh MOV AL, 01h OUT DX, AL ; select logical device 1 ; MOV DX, 2Eh MOV AL, F0H OUT DX, AL ; select CRF0 MOV DX, 2Fh MOV AL, 3Ch OUT DX, AL ; update CRF0 with value 3CH ;-----------------------------------------; Exit extended function mode | ;-----------------------------------------MOV DX, 2Eh MOV AL, AAh OUT DX, AL
6.4 Global Registers
CR02 (Default 00h, write only) Bit [7:1]: Reserved. Bit 0: SWRST =0 =1 CR07 (Default 00h) Bit [7:0]: Logical Device Number. CR20 (read only) Bit [7:0]: Device ID number (higher byte). = 71h
The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners
Normal operation. Software reset.
12
Publication Release Date:Jul. 2002 Revision 1.0
W83L518D
CR21 (read only) Bit [7:0]: Device ID number (lower byte) = 1Xh = 2Xh (for W83L518D) (for W83L519D)
X: Revision number CR22 (Default 80h) Bit 7: SCPWD =0 =1 Bit 6: MSPWD =0 =1 Bit 5: SDPWD =0 =1 Power down SD memory card interface. No Power down. Power down Memory Stick interface. No Power down. Power down Smart Card interface. No Power down.
Bit [4:0]: Reserved. CR23 (Default 00h) Bit 7: PME_EN. Power management event enable bit. =0 =1 PME_L function is disabled. Enable to issue a low pulse on PME_L when a power management event occurs.
Bit 6: MSPME_EN. Memory Stick interface power management event enable bit. =0 Memory Stick interface power management event is disabled.
= 1 Enable Memory Stick interface power management event to issue a low pulse on PME_L when PME_EN is also enabled. Bit 5: SDPME_EN. SD memory card interface power management event enable bit. =0 SD memory card interface power management event is disabled.
= 1 Enable SD memory card interface power management event to issue a low pulse on PME_L when PME_EN is also enabled. Bit 4: SCPME_EN. Smart Card interface power management event enable bit. =0 Smart Card interface power management event is disabled.
= 1 Enable Smart Card interface power management event to issue a low pulse on PME_L when PME_EN is also enabled. Bit [3:0]: Reserved.
The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners
13
Publication Release Date:Jul. 2002 Revision 1.0
W83L518D
CR24 (Default 00h) Bit 7: Reserved. Bit 6: MSPME_STS. Memory Stick interface power management event status bit. =0 No Memory Stick interface power management event occurs.
= 1 Memory Stick interface power management event occurs. Bit 5: SDPME_STS. SD memory card interface power management event status bit. =0 No SD memory card interface power management event occurs.
= 1 SD memory card interface power management event occurs. Bit 4: SCPME_STS. Smart Card interface power management event status bit. =0 No Smart Card interface power management event occurs.
= 1 No Smart Card interface power management event occurs. Bit [3:0]: Reserved. CR26 (Default 40h) Bit 7: Reserved Bit 6: HEFRAS, Extended Function Register Address Select. The corresponding power-on setting pin is GP10 (PHEFRAS, pin 14). The HEFRAS is defaulted to "1" if PHEFRAS is "0" and is defaulted to "0" if PHEFRAS is "1". =0 =1 Extended Function Registers are at 2Eh/2Fh. Extended Function Registers are at 4Eh/4Fh.
Bit 5: LOCKREG =0 =1 Enable accesses of Configuration Registers. Disable accesses of Configuration Registers.
Bit [4:0]: Reserved CR29 (Default 00h, only valid in W83L518D) Bit 7: Multi-function selection bit for pin 7 ~ 14 =0 =1 Pin 7 ~ 14 function as Smart Card interface socket B. Pin 7 ~ 14 function as GPIO1.
Bit 6: Multi-function selection bit for pin 35 ~ 43 =0 =1 Pin 35 ~ 43 function as MSI/SDI socket B. Pin 35 ~ 43 function as GPIO2.
Bit 5: Multi-function selection bit for pin 32 ~ 31 & pin 29 ~ 24. =0 =1 Pin 32 ~ 31 and pin 29 ~ 24 function as MSA (MS interface card A). Pin 32 ~ 31 and pin 29 ~ 24 function as SDA (SD interface card A).
Bit 4: Multi-function selection bit for pin 43 ~ 41 & pin 39 ~ 35. =0 Pin 43 ~ 41 & pin 39 ~ 35 function as MSB (MS interface card B). 14
Publication Release Date:Jul. 2002 Revision 1.0
The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners
W83L518D
=1 Pin 43 ~ 41 & pin 39 ~ 35 function as SDB (MS interface card B).
Bit [3:0]: Reserved.
6.5 Logical Device 0 (Smart Card Interface)
CR30 (Default 0x00) Bit [7:1]: Reserved. Bit 0: Logical device active bit. =0 Logical device is inactive. =1 Activates the logical device.
CR60, CR61 (Default 0x00, 0x00) These two registers select Smart Card base address [0x100:0xFFF] on 8-byte boundary. CR70 (Default 0x00) Bit [7:4]: Reserved. Bit [3:0]: These bits select IRQ resource for Smart Card interface. CRF0 (Default 0x00) Bit 7: IRQ sharing control bit. =0 No IRQ sharing. =1 IRQ sharing.
Bit 0: SCPSNT_POL (Smart Card PreSeNT POLarity). SCPSNT polarity bit. =0 SCPSNT is active high. =1 SCPSNT is active low.
6.6 Logical Device 1 (Memory Stick Interface)
CR30 (Default 0x00) Bit [7:1]: Reserved. Bit 0: Logical device active bit. = 0: Logical device is inactive. = 1: Activates the logical device. CR60, CR61 (Default 0x00, 0x00) These two registers select MSI base address [0x100:0xFFF] on 8-byte boundary.
CR70 (Default 0x00) Bit [7:4]: Reserved. Bit [3:0]: These bits select IRQ resource for MSI.
The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners
15
Publication Release Date:Jul. 2002 Revision 1.0
W83L518D
CR74 (Default 0x04) Bit [7:4]: Reserved. Bit [3:0]: These bits select DRQ resource for MSI. CRF0 (Default 0x00) Bit [7:5] : Reserved. Bit 4: IRQ polarity control bit by level mode . = 0: IRQ is active high. = 1: IRQ is active low. Bit 3: IRQ polarity control bit by pulse mode. = 0: IRQ is active low. = 1: IRQ is active high. Bit 2: IRQ sharing control bit. = 0: No IRQ sharing. = 1: IRQ sharing. Bit 1: MS4 output polarity control bit. 0: MS4 output low. 1: MS4 output high. Bit 0: MS4 output enable bit. 0: MS4 output disable. 1: MS4 output enable.
6.7 Logical Device 2 (GPIO)
CR30 (Default 00h) Bit [7:3]: Reserved. Bit 2: Individual disable/enable bit for GPIO2. =0 =1 GPIO2 is disabled if bit 0 is also "0". GPIO2 is enabled.
Bit 1: Individual disable/enable bit for GPIO1. =0 =1 GPIO1 is disabled if bit 0 is also "0". GPIO1 is enabled.
Bit 0: Logical device disable/enable bit. =0 GPIO1 and GPIO2 are disabled/enabled dependent on bit 1 and 2 respectively.
Publication Release Date:Jul. 2002 Revision 1.0
The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners
16
W83L518D
=1 Activates GPIO1 and GPIO2.
CR60, CR61 (Both default 00h) Base address configuration registers: programmable at addresses from 0100h to 0FF8h on 4-byte boundary. Base address + 0 and base address + 1 are for GPIO1 as direction register and data register respectively while base address + 2 and base address + 3 are for GPIO2 as direction register a data nd register respectively. CRF0 (GP10 ~ GP17 direction register. Default FFh) When set to "1", respective GPIO port is programmed as an input port. respective GPIO port is programmed as an output port. CRF1 (GP10 ~ GP17 data register. Default 00 h) If a port is programmed to be an output port, its respective bit can be read/written and output to respective pin. If a port is programmed to be an input port, its respective bit reflects what is on respective pin. CRF2 (GP10 ~ GP17 inversion register. Default 00h) When set to "1", respective incoming/outgoing port value is inverted. When set to "0", respective incoming/outgoing port value is the same as in data register. CRF3 (GP20 ~ GP27 direction register. Default FFh) When set to "1", respective GPIO port is programmed as an input port. respective GPIO port is programmed as an output port. CRF4 (GP20 ~ GP27 data register. Default 00h) If a port is programmed to be an output port, its respective bit can be read/written and output to respective pin. If a port is programmed to be an input port, its respective bit reflects what is on respective pin. CRF5 (GP20 ~ GP27 inversion register. Default 00h) When set to "1", respective incoming/outgoing port value is invert ed. When set to "0", respective incoming/outgoing port value is the same as in data register. When set to a "0", When set to a "0",
The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners
17
Publication Release Date:Jul. 2002 Revision 1.0
W83L518D
6.8 Logical Device 3 (SD Memory Interface)
CR30 (Default 0x00) Bit [7:1]: Reserved. Bit 0: Logical device active bit. =0 Logical device is inactive. =1 Activates the logical device.
CR60, CR61 (Default 0x00, 0x00) These two registers select SD Card interface base address [0x100:0xFFF] on 8-byte boundary.
CR70 (Default 0x00) Bit [7:4]: Reserved. Bit [3:0]: These bits select IRQ resource for SD interface. CR74 (Default 0x00) Bit [7:4]: Reserved. Bit [3:0]: These bits select DRQ resource for SD interface. CRF0 (Default 0x01) Bit [7:6]: Reserved. Bit 5: Set the output value of the DATA3 pin when bit4 is setted 1. =0 =1 =0 =1 The DATA3 pin will output low. The DATA3 pin will output high. Set the DATA3 pin to bi-direction pin. Set the DATA3 pin to output pin.
Bit 4: Set the DATA3 (MS1 or MSB1) pin to output pin.
Bit 3: Reserved. Bit 2: Select the pole of the GP11 card-detect pin. =0 =1 When det ecting the low signal indicate the card is inserted and high signal indicate the card is extracted. When detecting the high signal incicate the card is inserted and low signal indicate the card is extracted. Don't use the GP11 pin to detect card. Use the GP11 (SCBPWR_L) pin to detect card. Don't use the DATA3 (MS1 or MSB1) to detect card. Use the DATA3 (MS1 or MSB1) pin to detect card.
Publication Release Date:Jul. 2002 Revision 1.0
Bit 1: Select GP11 pin to detect card. =0 =1 =0 =1
Bit 0: Select DATA3 pin to detect card.
The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners
18
W83L518D
CRF1 (Default 0x01) Bit [7:4]: Reserved. Bit 3: Set the IRQ pole for level mode. =0 =1 =0 =1 =0 =1 =0 =1 The IRQ is active high. The IRQ is active low. The IRQ is active low. The IRQ is active high. The IRQ is level mode. The IRQ is pulse mode. No debouunce. Use debounce function.
Bit 2: Set the IRQ pole for pulse mode.
Bit 1: Set the IRQ to level mode or pulse mode.
Bit 0: Use debounce function for card-detect circuit.
7
ORDERING INSTRUCTION
PART NO. W83L518D PACKAGE 48-pin LQFP REMARKS
8
HOW TO READ THE TOP MARKING
SMART@IO
W83L518D 201GBSB
1st line: Winbond logo and the SMART@IO Trademark 2nd line: The chip part number. 3rd line: Tracking code 201 G B SB 201: packages made in '02, week 01 G: assembly house ID; O means OSE, G means GR, ... BSB: IC revision
The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners
19
Publication Release Date:Jul. 2002 Revision 1.0
W83L518D
9 PACKAGE DRAWING AND DIMENSIONS
Package- 48-pin LQFP
HD D A A2
36 25
A1
37
24
HE E
48
13
1
e
b
12
c SEATING PLANE
Y L1
L
:
Symbol
Dimension in inch Dimension in mm
Min Nom Max
0.002 0.004 0.053 0.006 0.004 0.272 0.272 0.014 0.350 0.350 0.018 0.055 0.008 0.006 0.276 0.276 0.020 0.354 0.354 0.024 0.039 0.004 0 7 0.006 0.057 0.010 0.008 0.280 0.280 0.026 0.358 0.358 0.030
Min Nom Max
0.05 1.35 0.15 0.10 6.90 6.90 0.35 8.90 8.90 0.45 0.10 1.40 0.20 0.15 7.00 7.00 0.50 9.00 9.00 0.60 1.00 0.10 0 7 0.15 1.45 0.25 0.20 7.10 7.10 0.65 9.10 9.10 0.75
A A1 A2 b c D E e HD HE L L1 Y 0
The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners
20
Publication Release Date:Jul. 2002 Revision 1.0
W83L518D
Headquarters
No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886 -35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852 -27516023-7 FAX: 852-27552064
Winbond Electronics (North America) Corp.
2727 N orth First Street San Jose, California 95134 TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
9F, No. 480, Rueiguang Road, Neihu District, Taipei, 114, Taiwa n TEL: 886-2-81777168 FAX: 886-2-87153579
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale.
The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners
21
Publication Release Date:Jul. 2002 Revision 1.0
W83L518D
10 THE W83L518D SCHEMATIC
XOUT R12 10 1 SCAC8 SCAC4 1 R14 10 SDCLK 1 2 SDPWCTL# SDLED SCC4 SCC8 MSLED MSPWCTL# VSS MSCLK MS1 MS2 MS3 MS4 3VCC MSLED MSPWCTL# MS1 MS2 MS3 MS4 MS5 XIN XOUT XIN 2 3 SW SPDT MS[5:1] SCARST# SCAIO SCAPSNT SCAPWCTL# SCALED HEFRAS EX_CD 1 14 3VCC 2 C4 10P S1 1 C5 10P 2 36 35 34 33 32 31 30 29 28 27 26 25 2 MSCLK Y1 48MHz R13 1M 2 1
L1 2.2UH
The LC resonance circuit is used to filter base frequency of 3rd overtone crystal.
1 C6 4.7U 8 U2 OUT VCC 48MHZ 7 GND 3VCC SD_3VCC R20 330 R19 4.7K 1 D3 2 LED J2 + C8 1U D5 R24 330 LED SD4 SD3 SDCLK SD2 SD1 SD5 Q6 NPN R29 1M 11 8 7 6 5 4 3 2 1 9 Wr_Pt SD4 SD3 Vss2 SDCLK Vdd Vss1 SD2 SD1 SD5 SD_SOCKET EX_CD# 10 EX_CD 2 1 3 5 7 2 2 4 6 8 RP1 8P4R-4.7K 1 SD_3VCC C7 0.1U 1 3VCC 1 R21 10K Rev 0.4 of 2 3VCC 2 MOSFET P Q3 R28 2 10K 1K R30 SDLED
SDLED SDPWCTL# SD1 SD2 SD3 SD4 SD5 LAD3 LAD2 LAD1 LAD0 SERIRQ LFRAME# PCIRST# PCICLK LDRQ# LFRAME# LRESET# PME# VSS GP17 GP16 GP15 GP14 GP13 GP12 37 38 39 40 41 42 43 44 45 46 47 48 SDCLK SD1 SD2 VDD3V SD3 SD4 SD5 LAD3 LAD2 LAD1 LAD0 SERIRQ MS5 XIN XOUT SCRST# SCIO SCCLK SCPSNT SCPWCTL# SCLED VDD GP10/HEFRAS GP11/EX_CD 24 23 22 21 20 19 18 17 16 15 14 13
SD[5:1]
U1 W83L518D_SB (LPC)
5VCC
LAD[3:0]
R15 10 2 SCACLK
5VCC R16 4.7K 1 2
HEFRAS 1 2 3 4 5 6 7 8 9 10 11 12
Power-on strapping for 2E/2F (Config. Port)
PME# PCICLK 1
R17 10 2
SD Socket (1) Circuit.
R18 33 1 SDPWCTL#
SC Socket (1) Circuit.
5VCC 2 1 SCA_VCC C9 0.1U R26 4.7K SCARST# SCACLK SCAC4 + C10 J3 1U 1 2 3 4 9 R31 1 4.7K 2 C1 C2 C3 C4 S1 SC_SOCKET 1 C5 C6 C7 C8 S2 5 6 7 8 10 5VCC SCA_VCC R32 330 2 D6 LED 2 MOSFET P Q4 SCA_VCC SCALED 1 SCA_VCC R22 330 LED R25 1K 2 Q5 NPN D4
R23 33 SCAPWCTL# 1
SC read/write LED
SCA_VCC 1
Soft start to protect MOSFET(Optional)
SD_3VCC
R27 20K
Soft start to protect MOSFET(Optional)
SCAPSNT
2
SCAIO SCAC8
inbond
Title Size B Date:
The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation
Publication Release Date:
WINBOND ELECTRONICS CORP. Document Number W83L518D Recommend Circuit Tuesday, February 26, 2002
Jul..2002
The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners
Revision 1.0
Sheet 2
22
W83L518D
The W83L518D Schematic
MS_3VCC
Memory Stick Socket (1) Circuit.
R2 33 MSPWCTL# 1 2 1 Q1 C1 0.1U 2 MOSFET P R3 + C2 4.7K 3VCC MS_3VCC 3VCC 1
R1 330 2 D1 LED J1 1 2 3 4 5 6 7 8 9 10 MS_SOCKET
Winbond Recommended Reader Board <>
R_JP1,2: 1x10 ; 2.0 mm(pitch) R_J1 : 2x5 ; 2.54 mm(pitch)
Soft start to protect MOSFET(Optional)
1U MS1 MS2 MS3 MS4 MS5 MSCLK D2
PIN 1
(R_JP2)
PIN 10
PIN 1
(R_JP1)
PIN 10
MSA_3VCC R4
330 LED R6 1K
(OPTION:reserved for power-down)
Q2 NPN
1 R5 C3 200K 0.1U 2
MSLED
1
2
10 PIN 6 PIN 1 2 5 (R_J1)
MS read/write LED
Extension Connectors
3VCC SD1 SD2 SD3 SD4 SD5 SDCLK SDPWCTL# SDLED JP1 1 2 3 4 5 6 7 8 9 10 3VCC 1 R7 1M SD4 2 2 1 SD1 R8 1M
The Note 1:
Note Note
SD1 SD2 SD3 SD4 SD5 SDCLK SDPWCTL# SDLED
Note
3VCC 1 R9 1M 1 MS1 R10 1M 2
Note
3VCC MS1 MS2 MS3 MS4 MS5 MSCLK MSPWCTL# MSLED MS1 MS2 MS3 MS4 MS5 MSCLK MSPWCTL# MSLED
RESET# should be connected with a low asserted signal like PCIRST# on PCI bus or LREST#on LPC bus(active low) There is either function of SD and MS can be used on versio A but two 2: sockets interface can be implemented on version B. If 3: any of SC or MS/SD function isn't intened to use, signals like SCPSNT/SCBPSNT should be tied to a pull-down resistor and MS[5:2]/SD[5:2] to pull-high resistors.These will reduce power consumption. (recommended: 4.7K-8.2K Ohm ) The trade marks and intellectual property rights of Memory Stick belong to SONY 4: Corporation.Information check: http://www.memorystick.org If 5: JP1,2,3,4 are designed for Winbond recommended reader please meet following connector spec. JP1,2: 1X10;pitch(2.0mm) JP3: 2X5 ;pitch(2.54mm)
JP2 1 2 3 4 5 6 7 8 9 10
MS4 2
For Note 6:
There Note (Ver 0.1 7:
SCAPSNT R11 1M 2
the recommended reader, please contact to Taiwan Zetatronic Industrial CO.,LTD(http://www.tzt.com.tw) are some difference as following from previous version: --> Ver 0.2) (1)Added circuit(GP10/EX-CD)to implement to sockets with external card detection pin. (2)Modified pulled-high resistor for write_protect detection from 500 ohm to 4.7K ohm. (3)Added configuration port selection pin(GP10/HEFRAS) by power-on strapping. (Ver 0.2 --> Ver 0.3) (1)Added power-on strapping circuit of different configuration port.(2E/2F) (2)Modified pull-down resistor tied to SD1 from 200K ohm to 1M ohm. (Ver 0.3 --> Ver 0.4) (1)Modified some erroneous netname like SCPWR#,MSPWR# and SDPWR#. (2)DMA transaction cannot be supported in this version.
5VCC SCAPWCTL# SCAC4 SCAIO SCACLK JP3 1 2 3 4 5 6 7 8 9 10 SCARST# SCALED SCAC8 SCAPSNT
SCAPWCTL# SCAC4 SCAIO SCACLK
SCARST# SCALED SCAC8 SCAPSNT
1
inbond
Title Size B Date:
The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation HEADER 5X2
Publication Release Date: WINBOND ELECTRONICS CORP.
Document Number W83L518D Recommend Circuit Rev 0.4 of 2
Jul..2002
The trademarks and intellectual property rights of SD belong to SD GROUP All trademarks and brand names belong to their respective owners
Revision 1.01 Tuesday, February 26, 2002 Sheet
23

▲Up To Search▲

Price & Availability of W83L518D

	To Download W83L518D Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .